FPGA Analyzer

The FPGA analyzer is a graphical tool that we used to perform synthesis on our designs. The main window shown in Figure 3.1 is invoked with fpga_analyzer command. In this window you can view the compiled design, perform timing and area analysis, and run the synthesis process. The FPGA analyzer also includes state-machine features that were not explored to their full potential during the course of our project. You can use the state-machine extraction features to isolate the state-machine from the entire design and set attributes such as encoding to the state machine. These features are described in SOLD manual.

  

Figure 3.1: Main FPGA analyzer window

From the main FPGA analyzer window, you can also invoke a command window and issue all instructions through a command line. After a while, this option proves to be faster because you can run numerous script files that get executed much faster. Eventually, we performed the entire synthesis by executing script files. This enabled us to invoke many synthesis sessions resulting in faster turnaround cycle.