Setting Initial Constraints

Setting design constraints is an important part of the synthesis process and should not be omitted at this point. Few constraints shown here are very basic and the reader is encouraged to look in other documentation such as the SOLD manual, to learn about the full capabilities of Synopsys constraints. Besides setting a clock period constraint, the designer can also put restrictions on paths that are known to result in long delays. By doing this, Synopsys tool will work extra hard to optimize all modules in that path in order to meet a path constraint. In addition to timing constraints, you can also put area restrictions on particular block of the design to further optimize the final netlist. Below is a brief example of setting some typical constrains in the script file.

/* Set the current design to the top level.        */
        current_design TOP
	remove_constraint -all
/* Uniquify the design and reset the schematic */
        uniquify
        create_schematic -size infinite -gen_database

/* include timming and area contraints */
	create_clock clk -period 100
	set_input_delay 0 -clock clk { all_inputs()}
	set_output_delay 0 -clock clk { all_outputs()}
	set_operating_conditions WCCOM

/* Indicate which ports are pads.    */ 
        set_port_is_pad "*" 

	set_pad_type -no_clock all_inputs()
	set_pad_type -clock clk
        set_pad_type -slewrate LOW all_outputs()
        insert_pads

Besides the clock period constrains, input pad delay can be defined. In this example these delays are 0ns which means that all inputs are delayed by 0ns with respect to the clock input. Wire-load information and delays are contained in files provided by XILINX and are invoked by setting the operating conditions. In this example, we set worst-case-commercial (WCCOM) conditions as applied to the specific XILINX device. The last step of this script excerpt inserts virtual pads in the design so that Synopsys has information regarding input and output pad delays.