LogiBloX Issues

Since LogiBloX components are proprietary to XILINX, it is not necessary to synthesize them and the Synopsys tools are not needed for these components. In cases where the LogiBloX component is inside a larger design, you must set the dont_touch attribute on those blocks containing LogiBloX. The portion of the script shown below, identifies two modules with LogiBloX components and sets the dont_touch attribute on three distinct LogiBloX.

/* Set the current design to the reg_bank level.        */
        current_design F15
/* Don't touch the logiblox*/
        set_dont_touch (bank_i_*)

/* Set the current design to the HYBMULT level.        */
        current_design F23
/* Don't touch the logiblox*/
        set_dont_touch (BANK_REG_LE_*)
        set_dont_touch (BANK_REG_*)

First LogiBloX in contained inside component F15 which is the reg_bank module. Within the reg_bank module all instances of bank_i_* LogiBloX are identified with the dont_touch attribute. Similarly, two more LogiBloX instances are treated inside module F23 which is the hybrid multiplier.

By setting the dont_touch attribute on LogiBloX, the synthesis compiler will 'skip' these components when performing logic optimization and synthesis. The *.edn file that was placed in the working directory provides Synopsys with information that is used to estimate net delay and area utilization through the LogiBloX component. This however is only an estimate since the final results for a specific LogiBloX or macro is not available until after the place-and-route stage. From our experience, we have seen that area estimate given by Synopsys for a design that contains LogiBloX is quite accurate (within 10% of actual). Timing results are heavily dependent on the availability of routing resources inside a particular device. Therefore, Synopsys approximation of timing delay and minimum clock frequency tend to be little too optimistic when LogiBloX components are included. In any case, reports generated by Synopsys provide a very good rough estimate of speed and area performance that can be used by the designer to identify critical paths before committing the design to the next stage which tends to be very time consuming.