Reading Design Components

Before you can compile the design, it has to be read into the analyzer. Some files may already be in acceptable format in which case you only need to read them. This is the case with the *.edn files that represent the LogiBloX components. These components are read in from the working directory. The *.edn files are created by the LogiBloX generator by producing the gate-level EDIF netlist as shown in Figure 2.1. The created *.edn files have to be placed in the working directory in order for the synthesis process to be able to read the LogiBloX components.

/* Analyze and Elaborate the design file.       */
        analyze -format vhdl "vhdl/" + F1 + ".vhd"

        read -format edif "WORK/" + F2 + ".edn"
        read -format edif "WORK/" + F3 + ".edn"
        read -format edif "WORK/" + F4 + ".edn"

        analyze -format vhdl "vhdl/" + F5 + ".vhd"
        analyze -format vhdl "vhdl/" + F6 + ".vhd"
        analyze -format vhdl "vhdl/" + F7 + ".vhd"
        analyze -format vhdl "vhdl/" + F8 + ".vhd"
        analyze -format vhdl "vhdl/" + F9 + ".vhd"
        analyze -format vhdl "vhdl/" + F10 + ".vhd"
        analyze -format vhdl "vhdl/" + F11 + ".vhd"
        analyze -format vhdl "vhdl/" + F12 + ".vhd"
        analyze -format vhdl "vhdl/" + F13 + ".vhd"
        analyze -format vhdl "vhdl/" + F14 + ".vhd"
        analyze -format vhdl "vhdl/" + F15 + ".vhd"
        analyze -format vhdl "vhdl/" + F16 + ".vhd"
        analyze -format vhdl "vhdl/" + F17 + ".vhd"
        analyze -format vhdl "vhdl/" + F18 + ".vhd"
        analyze -format vhdl "vhdl/" + F19 + ".vhd"
        analyze -format vhdl "vhdl/" + F20 + ".vhd"
        analyze -format vhdl "vhdl/" + F21 + ".vhd"
        analyze -format vhdl "vhdl/" + F22 + ".vhd"
        analyze -format vhdl "vhdl/" + F23 + ".vhd"
        analyze -format vhdl "vhdl/" + TOP + ".vhd"
        elaborate TOP

The rest of the component have come in the VHDL form. These pieces have to be analyzed to check for syntax and major design errors (such as multiple nets connected error). The order in which the files are analyzed does matter and elements in the lowest level of the design hierarchy have to be analyzer first. Consequently the top/system level file is analyzed last.