Generating LogiBloX Primitives

LogiBloX components were the most widely used macros in our designs. With the available tools from Xilinx, it is possible to generate netlist files as well as simulation primitives for storage components, ALUs, shift registers and many other function blocks. By using LogiBloX components for a specific function, you can ensure most optimal implementation of that function for a specific device. Since LogiBlox modules generate your netlist, synthesis of these components is not necessary.

In order to verify a design that contains LogiBloX, it is necessary to use the logiblox_design.vhd file that is generated by the Xilinx tools. Figure 2.1 shows the setup taplate used to create LogiBloX components.

  

Figure 2.1: LogiBloX setup template

It is essential that the user creates the simulation netlist in the for of a VHDL file and an implementation netlist as the *.ngo file. The simulation netlist is then used with the Synopsys simulator as described in Section 2.4. Similarly, the implementation netlist (*.ngo) is used during the place-and-route process to phisicaly realize desired functionality.