Compiling Simulation

Simulation can be done in interpreted or compiled mode. Compiled mode requires the C Developers bundle for HP that was not available to us. In compiled mode simulation, debugging becomes faster and easier because the VHDL design is converted to a C model. Consequently, we used the -i option to compile our VHDL design in interprative mode. Using this mode you need to ensure that you also compile logiblox.vhd, mvlarith.vhd, and mvlutil.vhd. files when using LogiBloX component in the design These are library files that have to be compiled in the iterpreted mode as well. Before you can compile these library files, you need to change the library declarations in your LogiBloX simulation netlist, and the library files. For example, the simulation netlist originaly tries to call the logiblox.vhd, mvlarith.vhd, and mvlutil.vhd files from the logiblox library:

LIBRARY logiblox;
USE logiblox.mvlutil.ALL;
USE logiblox.mvlarith.ALL;
USE logiblox.logiblox.ALL;

This has to be changed since you are trying to use the libraries that you already compiled in your work directory. Thus the above must be changed to:

--LIBRARY logiblox;
USE work.mvlutil.ALL;
USE work.mvlarith.ALL;
USE work.logiblox.ALL;

Now the libraries that will be used are compatible with the latest version of the simulation compiler and can be used in interpreted mode.

A sample script file that compiles all design components is shown below:

vhdlan -i mvlutil.vhd
vhdlan -i mvlarith.vhd
vhdlan -i logiblox.vhd
vhdlan -i dpmem.vhd
vhdlan -i reg.vhd
vhdlan -i reg_le.vhd
vhdlan -i mult2k4.vhd
vhdlan -i madd4.vhd
vhdlan -i const.vhd
vhdlan -i mult.vhd
vhdlan -i add2.vhd
vhdlan -i add3.vhd 
vhdlan -i bit_add.vhd
vhdlan -i SWITCH1.vhd 
vhdlan -i SWITCH2.vhd
vhdlan -i SWITCH3.vhd
vhdlan -i SWITCH4.vhd
vhdlan -i SWITCH5.vhd
vhdlan -i DOUBLE_fsm.vhd
vhdlan -i ADD_fsm.vhd
vhdlan -i add_array_lower.vhd
vhdlan -i reg_bank.vhd
vhdlan -i add_bank.vhd
vhdlan -i HYBMULT.vhd
vhdlan -i IO_fsm.vhd
vhdlan -i system.vhd
vhdlan -i TB_SYSTEM.vhd

The order in which the files are compiled does matter and the files in the lowest level of design hierarchy tree as well as all library components must be compiled first. Performing this compilation requires that you have a working directory (usualy named WORK) in the simulation directory as well as the setup filed descibed previously. The vhdlan compiler checks only for syntax errors. In other words, your design may compile without errors but the simulation waveform will show incorrect functionality. Sometimes, the error may be very subtle or hard to find even when using the waveform simulator and debugger. At this point it may be necessary to perform synthesis just to find out the source of the error.