Testbench Requirements

Synopsys VHDL simulation tools (vhdlan and vhdldbx) can simulate VHDL test-bench files. This was found to be the easiest way in which to apply stimulus during our projects. The most primitive test-bench file may contain a clock generator, design instantiation, and manual stimulus assignments. The test-bench shown below instantiates the final design and applies the stimulus manualy:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use work.array_types.all;

--
-- VHDL Architecture Test-bench
--
-- Created:
--          by - mrosner.mrosner (pike.WPI.EDU)
--          at - 16:45:58 09/15/97
--
entity SYSTEM_TESTBENCH is
--ENTITY OF A TEST-BENCH IS EMPTY
end SYSTEM_TESTBENCH;

ARCHITECTURE TEST OF SYSTEM_TESTBENCH IS

-- Architecture declarations
        CONSTANT clk_prd : time := 50 ns;
        constant width            : positive := 8; -- bits in signle register
        constant slices           : positive := 21; -- number of registers in array
        constant depth            : positive := 4;
        constant trinomial_coeff  : positive := 2; -- (k) from p. 158 in Menezes
        constant block_size       : positive := 7;

        SIGNAL clk             : std_logic ;
        SIGNAL reset           : std_logic ;
	SIGNAL START_JOB	: std_logic;
        SIGNAL input_coord_pin  : input_slice_array;
	SIGNAL mult_vector	: std_logic_vector((slices*width)-1 DOWNTO 0);

        SIGNAL ram_out          : slice_array;
	SIGNAL ready 		: std_logic ;

        SIGNAL iclk : std_logic;

        PROCEDURE wait_clock(CONSTANT clk_ticks:integer) IS
        VARIABLE i : integer := 0;
        BEGIN
                FOR i IN 1 TO clk_ticks*2 LOOP
                        WAIT UNTIL iclk'EVENT;
                END LOOP;
        END wait_clock;


        component system
                PORT( 
                        clk             : IN     std_logic ;
                        reset           : IN     std_logic ;
	                START_JOB	: IN	std_logic;
                        input_coord_pin : IN    input_slice_array;
	                mult_vector	: IN	std_logic_vector((slices*width)-1 DOWNTO 0);

                        ram_out         : OUT slice_array;
	                ready 		: OUT	std_logic 
                );
        end component;

BEGIN
   UUT : system
                Port Map (
                                clk => clk,
                                reset =>reset,
	                        START_JOB =>START_JOB,
                                input_coord_pin => input_coord_pin,
	                        mult_vector =>mult_vector,

                                ram_out =>ram_out,
	                        ready =>ready
                         );

   flow_process: PROCESS

   -- Process declarations
   VARIABLE j          : integer := 0;
   VARIABLE d_var      : unsigned(9 DOWNTO 0) := "0000000000";
   VARIABLE b_var      : unsigned(3 DOWNTO 0) := "0000";

   BEGIN
      input_coord_pin(0) <= "00110011";
      input_coord_pin(1) <= "00110011";
      input_coord_pin(2) <= "00110011";
      input_coord_pin(3) <= "00110011";
      input_coord_pin(4) <= "00110011";
      input_coord_pin(5) <= "00110011";
      input_coord_pin(6) <= "00110011";


      mult_vector <= "1011011010110110101101101011011010110110101101101
                      0110110101101101011011010110110101101101011011010
                      1101101011011010110110101101101011011010110110101
                      101101011011010110110";
      reset <= '1';
      wait_clock(1);
      reset <= '0';
      START_JOB <= '1';
      wait_clock(1);
      START_JOB <= '0';
      wait_clock(6);
      input_coord_pin(0) <= "10011001";
      input_coord_pin(1) <= "10011001";
      input_coord_pin(2) <= "10011001";
      input_coord_pin(3) <= "10011001";
      input_coord_pin(4) <= "10011001";
      input_coord_pin(5) <= "10011001";
      input_coord_pin(6) <= "10011001";

      wait_clock(6);
      input_coord_pin(0) <= "01110111";
      input_coord_pin(1) <= "01110111";
      input_coord_pin(2) <= "01110111";
      input_coord_pin(3) <= "01110111";
      input_coord_pin(4) <= "01110111";
      input_coord_pin(5) <= "01110111";
      input_coord_pin(6) <= "01110111";
      wait_clock(3);

      wait;
   END PROCESS flow_process;

        -- Architecture concurrent statements
        clock_gen : PROCESS
        BEGIN
                iclk <= '0';
                WAIT FOR clk_prd/2;
                iclk <= '1';
                WAIT FOR clk_prd/2;
        END PROCESS clock_gen;
   clk <= iclk;

END TEST;

The other option is to write a test-bench the read stimulus from a file and assigns it to corresponding signals. Furthermore, the test-bench can compare the output of the stimulus to results gathered through different means. In our case, the designs were modeled in C and the results from the C simulation were compared against the test-bench results.