Waveform Analisys and Debbuging

Once the source files are sucessfully compiled, the debugger can be invoked by typing vhdldbx &. This tool is a graphical debugging and waveform analysis application. The first step is to choose the configuration primitive associated with the test-bench. As shown in Figure 2.2, in our example the configuration file is CFG_TB.

  

Figure 2.2: VHDLDBX start menu

The configuration mapping is usualy defined at the end of the test-bench file as shown below:

configuration CFG_TB of SYSTEM_TESTBENCH is
        for TEST
                for UUT : system
                        use configuration WORK.CFG_SYSTEM_RTL;
                end for;
        end for;
end CFG_TB;

The above definition ensures that a correct configuration file is used for the component instatiated in the test-bench file (top level file). For more information on configuration definition and its uses, please refer to the SOLD manual.

Once the configuration is picked, the main debugger window is invoked. This window is shown in Figure 2.3.

  

Figure 2.3: VHDLDBX debugger

This window shows all your source code and signals that are implented. You can place break points in all reasonable places in the code and step through the VHDL processes. It is also possible to write script files for the debugger and run then in this window. This feature is quite usefull during pos-place-and-route verification stage as the signals become buried and hard to find graphically.

The waveform viewer can be invoked with the trace signal_name arguement in the debugger or through the hierarchy browser shown in Figure 2.4. This tool is invoked from the Misc menu in the debugger.

  

Figure 2.4: VHDLDBX hierarchy browser

The hierarchy browser proved to be quite usefull when searching for signals buried very deep in the design. The speed of this tool however is not very impressive for large designs simulated after place-and-route stage. One reason for this is because everything is compiled in interpreted mode. Thus using the compiled mode and the C Developers Bundle for HPs should speed-up the simulation process.

The traced signals can be viewed and the test-bench results can be compared with other design models. This is the last step of this stage after which the designer should be confident that the design functions logicaly. This step does not ensure that final product will work as the timing characteristics can only be verified after the place-and-route method.