/* Synthesize the design.*/
/* compile -map_effort high -ungroup_all*/
compile -boundary_optimization -map_effort high
All of these options and more are explained in the SOLD manual and perhaps the
most important ones are -map_effort and -boundary_optimization.
With boundary optimization turned on, the compiler with merge all components into one
file and perform optimization across all boundaries inside the top-level design. Synthesis
will take longer with this option turned on, however it may result in better performance as well.
If the designer knows exactly how to partition the design, boundary optimization may be
turned off. In this mode, Synopsys will optimize all individual components of the design
separately and then merge the results to generate the netlist. As long as the critical
path does not span over boundaries, turning off boundary optimization may result in
faster synthesis and better performance. The boundary optimization feature does not apply to
LogiBloX as we've already place a dont_touch attribute on these blocks.
The following includes some shell commands that perform some cleanup of older reports, as well as the commands that generate new timing, area, and constraint reports.
/* Write the design report files. */
sh rm -f "reports/" + TOP + ".old"
sh cat "reports/" + TOP + ".fpga" "reports/" + TOP + ".timing" "reports/" + TOP + ".cnst" > "reports/" + TOP + ".old"
report_fpga > "reports/" + TOP + ".fpga"
report_timing > "reports/" + TOP + ".timing"
report_constraint -verbose > "reports/" + TOP + ".cnst"
The result of these actions are three files containing new reports in the report directory,
as well as an old report that can be used to compare the results.
Synopsys synthesis is performed at the FPGA level. This means that the design is optimizes not at the gate level but at the CLB or logic block level. The advantage of such optimization is obvious as we are trying to fit the design into a device that contains only CLBs as digital elements. Thus, since Synopsys has detailed information about CLBs from libraries defined earlier, it can perform synthesis at this level. The design should be saved after compiling to preserve the CLB level netlist. This netlist can be used to extract state-machines, generate reports, and perform path and critical timing analysis. This netlist cannot be used however as an input to the XILINX tools. In order for XILINX to be compatible with many different synthesis tools, the vendor requires the netlist to be in gate level format. This can be obtained by running the replace_fpga command.
/* Write out an intermediate DB file to save state */
write -format db -hierarchy -output "db/" + TOP + "_compiled.db"
/* Replace CLBs and IOBs primitives (XC4000E/EX/XL only) */
replace_fpga
The resulting design and the netlist
are saved
/* Set the part type for the output netlist. */
set_attribute TOP "part" -type string part
/* Write out the intermediate DB file to save state*/
write -format db -hierarchy -output "db/" + TOP + ".db"
and the netlist is used in the place-and-route stage.
/* Save design in XNF format as <design>.sxnf */
write -format xnf -hierarchy -output "sxnf/" + TOP + ".sxnf"
Additionally, all constraints are save in a *.ncf file and used by the
place-and-route tools to optimize the design.
/* Write out the timing constraints */
ungroup -all -flatten
write_script > "dc/" + TOP + ".dc"
/* XILINX primitive to convert Synopsys design constraints to Xilinx format*/
sh dc2ncf "dc/" + TOP + ".dc"