Tools

The entire design, with the exception of vendor specific soft macros, can be entered in VHDL format. Once the design is developed in VHDL, boolean logic and major timing errors are verified by simulating the gate level description with Synopsys VHDL analyzer (vhdlan) version 1997.08. The next step involves synthesis of the VHDL code with Synopsys (fpga_analyzer) version 1997.08. The output of this step is an optimized netlist describing the gate level design in XILINX format. The most time consuming step is the compilation of the synthesized design with the place and route tools available from XILINX. The slow compile times associated with this step may result in a limited amount of data that could be gathered during this process. This step is accomplished with the XILINX Design Manager tools version M1.3.7. The next step of the design flow is to verify the design once again but this time with the physical net, CLB, and pad delays introduced when the design was placed into a specific device. This final stage of the design is accomplished with the same test benches and simulation models that are used during the logic verification stage. Synopsys (vhdlan) is used once again to verify back-annotated designs.