Simulation and Verification (PPR)

The Post-Place-and-Route (PPR) simulation and verification uses the same C model and test bench (with few modifications). The VHDL input model to this stage is different. Here the VHDL model is obtained from the XILINX place and route tools. This VHDL model looks nothing like the original one and it includes a separate file defining all net, CLB, and port delays associated with the placed design. Once again, verification process involves testing all vectors against the C model results using the Synopsys (vhdlan) tools. This process is described in detail in Chapter 5.