Place and Route

The place and route tools from Xilinx can be used on the HP workstation as well. Although by the time I leave WPI, I think that license will run out on the HPs. Besides, the compilation proved to be very slow is complex routing is required. Consequently, this step can be moved to a Windows environment so fast Pentium-based PCs could be used. This is not to say that this tool runs better in Windows. It is just that the availability of better hardware forced the migration to the Windows environment.

The input to the place and route tools is a design netlist and constraints files generated by Synopsys, as well as possible user constraints file. The user constraints have higher priority over the Synopsys constraints and may include additional constraints relaxing the clock period or implementing pin assignment. As stated before, the output of this process is a bit-stream file that can be used to directly program the device and the back-annotated design that can be simulated for timing verification (please refer to Figure 1.1). This process is described in detail in Chapter 4.