Xilinx Synopsys Interface

Figure 1.1 presents a flow chart diagram of the design flow with Xilinx-Synopsys-Interface (XSI) tools. The XSI tools provide for a transition between results obtained from Synopsys synthesis and the Xilinx place and route tools. The XSI module includes all libraries necessary for Synopsys fpga_analyzer to interpret gates into logical blocks so that synthesis can be performed at this level.

  

Figure 1.1: Design flow

The design_ware libraries provided by Xilinx are automatically instantiated when possible. For example, if the VHDL code contains addition ``+'' operations (such as the one used to increment counters), the Synopsys tool will utilize Xilinx design_ware libraries to instantiate soft macros for such adder units. Synthesis results include report files on area and timing utilization, design netlist and constraints that are used in the place and route process, and Synopsys design files that describe the entire system.