Simulation and Verification (RTL)

As previously stated, verification of the design is done at two points. First, it is applied to the initial VHDL design. This process is called the Register Transfer Level (RTL) simulation. This verifies only the logic without delays. The input to this verification process is a test bench written in VHDL, a model of the design written in C, and the actual VHDL design. The test bench is used together with the VHDL design to simulate the design. Then the results from the simulation are compared against results obtained from the C model. Logical verification is complete when all the test vectors are verified. This process is described in detail in Chapter 2.