The Process

The general design cycle that was adopted during my work will be described in detail in this manual. Assuming that the designer has conceived a digital design the next series of steps that will realize such design are described as follows:

1.

VHDL design entry.

2.

Logic verification of the design (RTL simulation).

3.

Synthesis and logic optimization.

4.

Device specific realization (place and route).

5.

Back-annotated verification of the design (PPR simulation).

6.

Optimization

7.

Implementation

Because of the vast array of reconfigurable devices available today, VHDL implementations tend to become vendor specific. This is due to the fact that many vendors provide soft macros for predefined components. These macros take advantage of specific features in a given device making it nearly senseless to build equivalent functions with VHDL. By choosing a specific family of devices, it was now possible to identify useful macros for the conceived design. Having the knowledge of these macros and the initial design, a digital system can be developed in VHDL with macro instantiations. This process requires the use of special libraries and will be described for the simulation and synthesis chapters of this manual.

Verification of the design is first performed on the logic level basis. This step assures the correct functionality of the design without the combinatorial and net delays. Once the design is verified logically, synthesis and optimization is performed. Timing constraints are set for each component and different iterations are done until constraints are met. The next step is to actually map, place and route the design into reconfigurable device. The choice of a specific device within the device family depends on the area utilization report obtained through synthesis. Finally, the output of the place and route step is used to perform back-annotated simulation. This step verifies the correct operation with net and combinatorial delays that results from the place and route process.