System Test-bench File

The test-bench file that you used during the RTL simulation can also be used at this stage. However, it is important to keep in mind that the post place-and-route simulation file time_sim.vhd may have different port definitions. This may occur when you have array structures or variables as inputs or outputs in your original VHDL code. After the place-and-route process variables, and arrays are changed to physical ports (signals) and thus the instantiation of your system in your system test-bench will no match the port declaration in the time_sim.vhd file. This is a minor change that you have to make.