Input Files

The two files generated by Xilinx M1 tools are time_sim.sdf, and time_sim.vhd. You will need these files in you simulation directory. The time_sim.sdf file contains all timing information that resulted from a specific place-and-route session. The time_sim.vhd is the simulation file that contains your design. This VHDL code looks nothing like the code you wrote because it is defined in terms of Xilinx CLBs and net connections. This means that it will be very hard and sometimes impossible to find the signals that you want to trace during this simulation.

In addition to your design files, some library components are needed. These are simprim_VITAL.vhd, simprim_Vcomponents.vhd, and simprim_Vpackage.vhd. These files contain library definitions of all function block found inside the Xilinx device and are called by your design file. The library files can be found in the Xilinx directory $XILINX/vhdl/src/simprims/. Normaly, these library files are compiled only once during instalation or upgarde of Synopsys tools and the compiled files would be accessed through the SIMPRIM library. This is not true in our case. The reason why we had to compile the simulation libraries every time is that we didn't have the appropriate C compiler on the HPs at that time. Consequently the libraries could not be generated with the following commands:

vhdlan -c -optimize -w SIMPRIM  $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd
vhdlan -c -optimize -w SIMPRIM  $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
vhdlan -c -optimize -w SIMPRIM  $XILINX/vhdl/src/simprims/simprim_VITAL.vhd.

Once the appropriate compiler is available, all necessary simulation libraries, including LogiBloX libraries, should be recompiled and stored permanently in the Xilinx directory.