Internal Global Buffers

The 4000 series devices also contain dedicated routing resources that can be used for high fanout signals. By using these resources you will ensure the smallest possible net delay for the high fanout signal. This is generally advantageous when the high fanout signal is in the critical path. Once again, a special component has to be instantiated in the VHDL code to ensure that the global routing resources are utilized. Example below shows such instantiation of BUFGS_F which is a XILINX library component.

--declare component
component BUFGS_F
              PORT ( I : IN std_logic;
                     O : OUT std_logic);
end component;

--instantiate component
FORCEBUF: BUFGS_F port map (I => in_clk_en,
                            O => clk_enable_hf);

Usually a clock enable signal exhibits high fanout. In the example above the clock enable signal in_clk_en is passed through the buffer BUFGS_F. The resulting clock enable line clk_enable_hf is the signal that should be used for a high fanout load. During RTL simulation, the BUFGS_F instantiation will cause a problem. That's because this component is not known to the simulation tool and the component drives many other modules. Thus, to perform RTL simulation, you need to comment out the BUFGS_F instantiation and connect in_clk_en directly to clk_enable_hf (clk_enable_hf<=in_clk_en).