Startup Block

The XC4000 device has a dedicated set/reset net that is routed to every flip-flop in every CLB in the device. Thus you do not need to utilize general purpose nets to route the reset signal to each flip-flop. This ensures fast path to all CLBs and frees additional routing resources that can be used for the rest of the design. The STARTUP block is a component defined in the XILINX library path that can be instantiated in the same way as any module inside your design. Thus you first declare the component

component STARTUP   
                PORT ( GSR : IN std_logic );
end component;

and then instantiate it inside the architecture body.

STARTUPBLK: STARTUP port map (GSR => reset_internal);

Your global reset signal is also fed to the GSR input of the STARTUP block. This ensures that the dedicated set/reset net is utilized during the place-and-route stage. The STARTUP block is defined only for the synthesis tools. This means that when you perform RTL simulation, you will receive a warning saying that the simulation compiler could not infer the STARTUP block. This will not change RTL simulation because the GSR is an input to the STARTUP block.