Simulation Script

The script file can contain all commands that you would normally use in the simulation debugger window. The most often used commands include trace, evaluate, cd, step, next and many more. For a full listing of commands you may want to invoke the help window from the simulation debugger. In any case, the trickiest part of post place-and-route simulation is trying to simulate the signals that you want. This is because your design file time_sim.vhd is rather large and contains signals for all nets in the routed design. On top of that, Xilinx M1 tools may have renamed some signal names, at which point you will have to refer to the Xilinx floor-planner to find the names of the nets that you want to simulate. In most part, the Xilinx tools are not so cruel and leave part of your signal and port names in the resulting net name. The best way to search for your signal names is to do an initial text search on the time_sim.vhd file. This should give you some idea as to the naming convention and allow you to find the signals in the floor-planner. After finding the signals, it is a matter of tracing them in the script file. When doing so, you should include the full path name through the hierarchy including the test-bench. For example, to trace signal a_op_s1(8,3) from your design you need to use the following command:

trace /system_testbench/uut/a_op_s1(8,3).

Or you can change into the design directory, cd /system_testbench/uut, and then trace only the signal name.

Comparing these simulation results to RTL simulation and a C model of the design finalizes this stage. At this point you are ready to implement you design on a piece of hardware by down-loading a file generated by the Xilinx M1 tools into an EPROM that can be later used to program the Xilinx device on start-up. More details on how that procedure should follow in the next chapter. If your design does not meet the specs, or does not work properly, you will need to turn back to Chapter 2 and perform the entire cycle again. Good Luck!