Placing and Routing Your Design

The main tool used during this process is the Foundation Series software M1.3.7. This was the latest version of XILINX place-and-route tools available for their devices. Figure 4.1 shows the main design manager window. The design manager allows you to compile many different versions of the design. Thus you can compile for different devices or with different timing constraints and different mapping and routing efforts.

  

Figure 4.1: Xilinx design manager

You may want to try initial place-and-route process using relaxed compiler settings. This will speed up the process and allow you to do post place-and-route verification of the design rather quickly during the early stages of this procedure. Once the design has been verified after the place-and-route process, you should run a final place-and-route with maximum efforts and better timing constrains. We have found that running through many iterations and tightening the clock constraint improves the performance of the design up to a certain limit.

There are quite a few options that you may choose before starting the place-and-route process. All of these options are explained in the Xilinx manual available from the ECE department. In addition you may reference the HDL Synthesis For FPGAs manual available from Xilinx WWW or in the Crypto Lab. If you are using the netlist constraint file generated by Synopsys, You will need to delete/comment out one line in that file. The file that reads

NET "clk" OFFSET = IN : 0 : AFTER : "clk\pagestyle{headings}
%***********************************************************************
\chapter{\label{chap:par}Place and Route}
%***********************************************************************
The place-and-route process was originally performed on the XILINX
tools installed on the HPs. This was a convenience because all tools
up to this point have been running on HPs as well. The HPs however
proved to be very slow and we had to migrate this process to the
PC. Even running on a 200MHz Pentium with 64M of RAM, the compilation
required days and even weeks. Needless to say this process is the
most time consuming one and the designer should be aware that
large designs will take quite a long time. The designer should be
fairly confident of the correct functionality of his/hers module
before committing to this stage of the process.

\section{Setup}
The M1 tools were run on PC and after installation minimal setup
was required. You should create a directory on the C drive
(working over the network slows down the process) and copy
the netlist files generated by Synopsys into that directory.
Xilinx tools will keep different revisions of the place-and-route
results in separate folders automatically.

\section{Input Files}
Xilinx tools can read *.edn and *.sxnf netlist formats.
Since Synopsys creates the *.sxnf file you will need to
use that as input to the Xilinx tools. In addition, if you
created a constraint file with Synopsys, you should use
it in the place-and-route stage as well. This is the *.ncf
or netlist constraint file, that contains clock, net, area,
and pad constraints. In addition to the netlist constraint
file you can specify your own constraints in the user constraint
file (*.ucf) and also use it as input to the Xilinx tools.
The *.ucf file takes priority over the *.ncf file so you can use it to
overwrite the constraints that you have set during synthesis.

\section{Placing and Routing Your Design}
The main tool used during this process is the Foundation Series
software M1.3.7. This was the latest version of XILINX place-and-route
tools available for their devices. Figure~\ref{fig:xilinx1} shows the
main design manager window. The design manager allows you to compile
many different versions of the design. Thus you can compile for different
devices or with different timing constraints and different mapping and
routing efforts.
\begin{figure}[h!]
\centering
\scalebox{0.72}{
\includegraphics*[0cm,0cm][14.75cm,10.62cm]{graphics/xilinx1.ps}
}
\caption{\label{fig:xilinx1} Xilinx design manager}
\end{figure}
You may want to try initial place-and-route process using relaxed compiler
settings. This will speed up the process and allow you to do post place-and-route
verification of the design rather quickly during the early stages of this procedure. Once the
design has been verified after the place-and-route process, you should run a final
place-and-route with maximum efforts and better timing constrains. We have found
that running through many iterations and tightening the clock constraint improves
the performance of the design up to a certain limit. 

There are quite a few options that you may choose before starting the place-and-route
process. All of these options are explained in the Xilinx manual available from the ECE
department. In addition you may reference the \textit{HDL Synthesis For FPGAs} manual
available from Xilinx WWW or in the Crypto Lab. If you are using the netlist constraint file
generated by Synopsys, You will need to delete/comment out one line in that file.
The file that reads
\begin{small}
\begin{verbatim}
NET "clk" OFFSET = IN : 0 : AFTER : "clk";

should be changed to

#NET "clk" OFFSET = IN : 0 : AFTER : "clk";.

For some strange reason Synopsis creates an OFFSET definition for the clock with respect to the clock. Xilinx does not like that definition, and since it is not needed anyway, you should delete it. Figure 4.2 shows the menu where you can define different options, and constrains, and guide files. In order to do the post place-and-route verification using Synopsys, you must create a simulation file in the VHDL format as shown in Figure 4.2.

  

Figure 4.2: Implementation options menu

In the next chapter I will describe how to use this VHDL file to verify your final design. Some other options that you should pay attention to are the optimization and mapping settings, as well as the place and route configuration.

Figure 4.3 shows the flow engine that is invoked during the implementation stage of the place-and-route process. This window will update you on the progress of the compilation and show you any errors and warnings that may result in the different stages of the process. Some of the warnings that may come up should not cause great concern. Xilinx M1 posts warning when it finds logic_0 or logic_1 connections generated by Synopsis. These are just power and ground connections and the M1 tools know what to do with them. The M1 tools also generate warnings when signals are merged and blocks are optimized. This is normal.

  

Figure 4.3: Xilinx flow engine

When all stages of the compilation are completed without errors, the simulation VHDL file (time_sim.vhd), as well as the timing characteristics file (time_sim.sdf) are generated.