About This Manual

During the course of my MS thesis I had the less than pleasant opportunity to learn the tools used for VHDL synthesis, simulation and implementation. Together with a colleague of mine, Jens-Peter Kaps, we managed to set up libraries and run the appropriate tools in order to realize our designs. In this case, the word `realize' encompasses many stages of the development for which different tools had to be installed and utilized. The generous help of our sys-admin guys, Brady Schulman and Murtaza Amiji was crucial during this setup and installation stage. In this document, I will try to describe the process that we used to realize a conceivable digital design. This document is not intended to be 100$\%$ thorough and should be used as an initial guide to the synthesis, simulation and implementation tools. Most of the information presented here can be found in the online documentation provided by the vendors. My job here is just to summarize the most important and the hard to find information regarding the setup and utilization of these tools. For a more formal and more complete source of information, the reader is directed to the vast number of manuals that exist and are available online or in the crypto lab. Whenever appropriate, I will try to point out the particular documentation manual and describes a certain subject in greater detail.

In this chapter, I will give a general description of the process that we used to realize our designs. I will also briefly describe our main method of design entry and some of the more important considerations associated with VHDL entry and synthesis. Each consecutive chapter after this one will describe one step of the process and the tools associated with this step. Thus if you just want to learn about synthesis you should refer to Chapter 3 that describes the Synopsys tools that we used to perform synthesis.