RTL Verification

Register Transfer Level (RTL) simulation and verification is one of the initial steps that was done. This step ensures that the design is logically correct and without major timing errors. It is advantageous to perform this step, especially in the early stages of the design, because long synthesis and place-and-route times can be avoided when an error is discovered at this stage. This step also eliminates all the syntax errors from your VHDL code.

We used the Synopsys simulation tools to perform RTL verification. More specifically, vhdlan, or VHDL_analyzer was used. In addition, if the design contains LogiBloX components, (which is usually the case), the corresponding VHDL primitives generated by Xilinx tools along with Xilinx libraries have to be visible to the Synopsys tools. In the following I will describe the process of compiling/simulating a VHDL design that includes LogiBloX using VHDL_analyzer. An example of a test-bench VHDL file will be explained and simulated against the design. Finally, few debugging tips that we picked up along the way will be given.