The unifying principle behind this research is the development of design methodologies for mixed signal integrated circuits and systems. As the design of integrated circuits increases in complexity to become the design of integrated systems, it becomes more necessary to guide design by connecting system-level performance to fundamental limits imposed by circuit-level considerations, for example thermal and shot noise. The research described in this proposal follows from a simple design methodology that was developed with this overall philosophy in mind. This methodology has been extremely successful within the original set of tasks it addressed, which is the design of low noise integrated oscillators for use as the time/frequency reference in 155MHz data communication. Section I describes the original application of this design approach, as well as related areas which face similar design tasks and will benefit from an expansion of the design methodology. Section II describes the methodology and the design insights that follow from its unique approach.
Section III describes a relatively straightforward extension of the design methodology from 155MHz to 622MHz. This is a short-term project which is closely coupled to a particular data communication application. Preliminary work on this project has shown that, although the basic approach of the methodology is sound, some of the simplifying assumptions that hold at 155MHz are being stretched at 622MHz. To maintain confidence in the design methodology, further improvements in system performance must be accompanied by improvements in the design methodology. Section IV describes the necessary improvements in the design methodology. This is a long term project and is more research oriented, since it is not as closely coupled to a particular application. As will be seen, improvements in each of the areas of speed, power consumption, and process technology stress different aspects of the simple design methodology. It is expected that expanding the methodology in each of these areas will yield valuable insights for the design of low noise integrated systems.
The main application for which this work was originally done is serial data transmission over a fiber optic link. One example is the AT&T Synchronous Optical Network (SONET) standard [1]; another is the emerging Asynchronous Transfer Mode (ATM) protocol. This kind of system is shown conceptually in Figure 1 . To reduce interconnection hardware, only the data is transmitted over a single fiber link. At the receiving end of the link, the optical signal is converted to an analog voltage waveform by a transconductance amplifier. The function of the clock recovery circuit is to process the analog input voltage Vin and generate the corresponding bit clock RCLK. This recovered clock signal is used as the clock input to a D flip-flop, which samples Vin to develop the output serial data stream.
For this application, the measurement goal is to determine how well the clock recovery function can be performed. The timing diagram in Figure 1 shows the ideal case when clock recovery is performed perfectly: There is no phase error in the recovered clock, and RCLK samples Vin at the exact center of the bit period. This gives the minimum bit error rate (BER). Any deviation of RCLK from the ideal will increase BER.
Increased BER is not the only negative effect of jitter in serial data communication systems. In a repeatered system, where the recovered clock is also used as a transmit clock for a subsequent data link, phase jitter reduces the number of links that can be cascaded before jitter becomes unacceptably large [2].
In evaluating the performance of a data link, the end user must be concerned with many other possible influences on BER. Among other factors that can degrade system BER in a fiberoptic link are power loss and dispersion in the optical fiber, inadequate optical power input at the transmit end, and noisy optical-to-electronic conversion at the receive end.
To assess its contribution to BER, the clock recovery block can be tested independently, as shown in Figure 2 . The input is an ideal data waveform; the recovered clock is then compared to the transmit clock using a communications signal analyzer. If there were no jitter, the phase difference between the clocks would be constant (due only to static phase and propagation delay differences). In the presence of jitter, there is a distribution of phase differences. To estimate the distribution, the CSA compiles a histogram of phase measurements as shown in Figure 2. The standard deviation of this distribution is the end user's figure-of-merit for characterizing the jitter performance of the clock recovery block. Jitter errors are typically of order 1% of a unit interval; at a 155MHz data rate the unit interval is 6.4 nsec, so the jitter errors to be measured are of order picoseconds. Of course the time base stability of the measuring instrument must be better than the clock waveform that is being measured.
There are additional ways of measuring phase and phase errors. The phase noise power spectral density is a measure of stability in the frequency domain. In this case a spectrum analyzer or specialized phase noise measurement system is required. In properly functioning systems, the magnitudes of the phase noise measurements is quite small; typically of order -100dBc/Hz or lower.
One approach for generating the recovered clock is to use a phase-locked loop (PLL) [3-7] as shown in Figure 3 . This has the advantage of being integrable, and thus relatively inexpensive. In the PLL, the time reference for the recovered clock is provided by a voltage controlled oscillator (VCO). The design methodology described in section II was developed to connect fundamental, circuit-level noise sources to the system level instability of the VCO clock.
In addition to this work's relevance to serial data transmission systems, there are several other important system applications requiring low jitter performance from PLLs that perform a clock recovery function:
Disk drive clock recovery
Data is usually stored on magnetic media with no reference track to indicate bit boundaries.
Therefore when data is read from the magnetic medium, there is a need to recover a clock signal
from the data to determine the bit boundaries. Low jitter is necessary since any increase in jitter
increases read errors [8].
Generating high speed digital clocks on-chip
As digital processor and memory chips become capable of operating at clock rates exceeding 100
MHz, the problem of distributing such a high speed clock throughout a system becomes more
difficult. One approach to solving this problem is to distribute a lower frequency clock, and
multiply this clock to the higher frequency with an on-chip PLL [9]. Low jitter is necessary since
any increase in jitter reduces timing margin for digital signals that rely on the clock.
Oversampled Data Conversion
A PLL can be used to generate the high-speed clock required for delta-sigma A/D and D/A
conversion in digital audio applications. Low jitter is necessary since phase noise on the clock
can be aliased into the audio band to produce audible, objectionable artifacts in the reconstructed
analog waveform [10].
Wireless Communication
A PLL can be used to integrate the local oscillator (LO) function required for signal modulation
and demodulation in radio frequency (RF) communication ICs. In this case, frequency-domain
performance is important since phase noise on the LO will translate into noise in the signal band
after demodulation [11].
Three types of oscillator can be considered as candidates for the VCO: Harmonic, relaxation, and ring oscillators. A harmonic oscillator is characterized by an equivalence to two energy storage elements, operating in resonance, to give a periodic output signal. The actual resonant element might be an LC tank or a quartz crystal. Resonant circuit-based VCOs are known to have excellent jitter performance [12]. Unfortunately the requirement of an off-chip tank or crystal defeats the purpose of integrating the PLL function. Although integrated inductors have been reported in the GHz frequency range [13], these generally have low quality factor Q due to resistive losses, and in any case are not practical in the 100 MHz to 1 GHz frequency range. Analysis of noise in resonant-based VCOs is well developed in the literature, and design techniques for realizing low jitter performance have been well understood since the late 1950s [14-16]. In general, the noise analysis has been approached in the frequency domain, with the high Q of the circuit resonance filtering noise into a narrow band near the fundamental frequency.
A relaxation (multivibrator) oscillator is characterized by an equivalence to one energy storage element, with additional circuitry that senses the element state and controls its excitation to give a periodic output signal [17]. Fully integrated clock recovery PLLs have been described using multivibrator VCOs [6, 18-20]. In general, jitter analysis for this type of oscillator has been approached in the time domain [17, 21, 22]. The jitter performance of the multivibrator is known to be worse than the harmonic oscillator, although design techniques for improving jitter have been available since the early 1980s [17, 23, 24]. For fully integrated VCOs, there is a need for improvement of jitter beyond the best achieved by the multivibrator.
The third class of oscillator is the ring oscillator: a loop of N delay stages with a wire inversion, as shown in Fig. 3. The ring will oscillate with a period of 2N times the stage delay. Voltage controlled ring oscillators have frequently been explored as an alternative to the multivibrator for fully integrated, lower jitter clock recovery PLLs [3, 25-31]. Like the multivibrator, a ring oscillator is fully integrable. In addition, some of the empirical results show promise of excellent jitter performance [31]. However, prior to the development of the methodology described here, a survey of the literature showed that there had been no theoretical analysis of jitter in ring oscillators. Thus there were no techniques available for designing to achieve lower jitter in a ring oscillator. Perhaps one reason that analysis of jitter in ring oscillators has lagged is that the ring does not fit well into either of the harmonic or multivibrator oscillator models. The number of energy storage elements is not as explicit; in fact there are many "energy storage elements" since the ring is composed of multiple stages. Thus, a new approach was needed to give designers confidence in designing to achieve a given level of jitter performance.
The design methodology that fulfills this goal was developed by the author and verified in [4]. First a simple technique was developed to establish correspondence among time and frequency domain measures of jitter with the PLL loop open or closed. Relating time and frequency measures is important to ensure that the design methodology is relevant to all of the applications mentioned in section I above, since the effects of noise in limiting performance can be viewed in the time or frequency domain. Relating open-loop and closed-loop performance is important to simplify the design process, since an open-loop oscillator can be examined (and simulated) in isolation from other system components.
The key challenge that was addressed in developing the design methodology is connecting noise performance at four different levels of complexity, as shown in Figure 3: the overall clock- and data-recovery system, the phase-locked-loop within the clock recovery function, the delay stages in the PLL voltage controlled ring oscillator, and the individual circuit-level components within the delay stage. The major contribution of this approach is the identification of a time domain figure-of-merit that applies across all levels of complexity. At the system level, this figure- of-merit can be related to jitter performance as measured by the end-user in both the time and frequency domains. At the component level, the figure-of-merit is related to fundamental sources of jitter in the oscillator, such as thermal noise and shot noise. The result is a design procedure which gives explicit constraints on circuit elements (such as resistance and capacitance values and bias currents) as a function of desired jitter performance.
To keep the scope of the analysis manageable, the technique was developed in the context of a ring oscillator composed of differential-pair delay stages fabricated in a bipolar technology. To simplify the analysis and make the results easier to interpret, a number of assumptions were made:
The validity of these assumptions has been confirmed by test results on a family of 155MHz PLLs, which have been fabricated in a dielectrically isolated complementary bipolar process. The design procedure predicted the measured jitter performance to an accuracy of within 10%, which is excellent for predicting noise performance.
With these assumptions, the resulting design equations yielded significant intuitive insight into the effects of design choices on system-level noise performance. For example, it was discovered that there are straightforward, fundamental linkages between system level noise and circuit level considerations such as power dissipation and oscillator waveform amplitude. Additional confirmation of the validity of this approach was obtained by expressing the well known results of the harmonic and multivibrator design procedures in the form of this design methodology. The resulting expressions for the relationship between noise performance and fundamental power dissipation were similar for all three classes of oscillators. This is a strong indicator that this approach has promise to apply to the entire class of ring oscillators. The key question to be answered is: What will happen as assumptions 1 - 5 need to be modified or discarded as the methodology is extended?
UNIQUE FEATURES OF THIS APPROACH
There are several unique features of this general approach that show promise for further investigation in applications at higher speed, lower power, and in other fabrication technologies.
Successful theoretical description of a widely used class of oscillators
Until this approach was developed, there were no ring oscillator design techniques comparable to
those available for harmonic and multivibrator oscillators. Extension of this approach will
further enable confident design of high performance integrated oscillators for a wide variety of
important applications.
Relating noise performance over several levels of complexity
These techniques allow the designer to conduct analysis and synthesis at whichever level of
complexity is most convenient, while confidently being able to predict the ultimate system-level
jitter. For example, a full (transient analysis mode) simulation of the VCO would require an
inordinate amount of computer time due to the large number of components in the VCO circuit.
However, simulation at the gate level is tractable and provides valuable information which can be
related to system-level jitter performance.
Speed design by relating fundamental parameters to system level performance
The ability to traverse several levels of complexity, from system-level performance to circuit-
level constraints, is very valuable in the early stages of design when system level power and
performance budgets are being roughed out. For example, in the case of low power design, the
technique sets a limit on the best possible jitter that can be achieved for a given DC power
dissipation. Thus, even before proceeding with detailed circuit design, the designer knows
whether a given jitter performance goal can be achieved within a given power constraint. As
another example, the technique relates waveform amplitude and jitter. Thus in the case of low
supply voltage design (with little headroom for large signal swings), it is possible to immediately
determine the best possible jitter that can be achieved at a given signal amplitude.
Identification of individual contributions to jitter performance
The design procedure yields expressions for the absolute noise contributions from different
sources of jitter, allowing the designer to determine which source is the major contributor in a
given design. This is an essential part of simplifying the design process, which at the circuit level
involves many variables, for example transistor geometry, resistance and capacitance values, and
DC bias currents. Considering all the permutations of design decisions, there are literally
hundreds of design options available. The ability to identify which options are most effective in
reducing noise is tremendously valuable in speeding design.
Relating open loop and closed loop performance and measurements
The relationship between open-loop and closed-loop performance simplifies design by allowing
the designer to isolate VCO design as a separate task. In addition, the open-loop/closed- loop
relation is also useful in evaluation of actual devices. From open loop VCO measurements, we
can predict what the closed loop performance should be if limited only by the VCO jitter. Then
we can compare this prediction with actual measurements to determine if other PLL
components (such as the phase detector or loop filter) are degrading the closed loop
performance.
The following sections describe two projects that seek to extend the design insights developed in this approach. The first is a short-term project that is being funded by an industry sponsor and will be completed by the end of 1996; the second is long-term research that is the basis of the work being proposed to the CAREER program.
This research will investigate the applicability of the low-jitter design technique in a straightforward extension to a 622MHz VCO. Analog Devices Semiconductor, Inc., has already committed to fund a fellowship for graduate student time to perform this work.
This work will begin to investigate the applicability of the jitter theory at higher speeds. As mentioned previously, the design procedure has been used to design low-jitter VCOs in the 155MHz frequency range. The noise predictions of the theory have been quite good, within 10% of actual measurements. Some preliminary investigation at 622 MHz indicates that there will be some accuracy degradation as the simplifying assumptions begin to break down. How much accuracy degradation will there be at higher speeds, where some of the simplifying assumptions made in the theory may not apply? If there are high speed effects, can the theory be modified to take them into account?
As part of the fellowship support, Analog Devices has committed to provide some support in the area of test equipment - specifically, some time will be made available on a bit error rate (BER) tester to test performance in the particular data communication application. Although this is sufficient for Analog Devices' product development purposes, it is insufficient to verify the theoretical predictions in the frequency domain and across different levels of complexity. Due to the time and money constraints of the industry environment, there is no time available on general purpose test equipment to investigate the full implications of the design methodology.
It is essential to verify the methodology by fabricating and fully testing prototype chips that implement a system function. As indicated above, Analog Devices is supporting fabrication. However, since only "pass-fail" testing is being supported under the Analog Devices fellowship, NSF support is being requested for test equipment under the CISE Research Instrumentation Grant program. This will allow full testing of fabricated chips, and comparison of the measured performance to the predictions of the design methodology. This equipment will also be used in evaluating the integrated circuits designed and fabricated under the long-term research described below.
This work will extend this theoretical approach to much higher speeds (2.5GHz) as well as other applications and technologies. This is the research that is being proposed to the CAREER program, and is anticipated to require a four year time frame. Since this work is longer-term (more research-oriented than near-term product-oriented) it is less likely to be funded by industry.
The goal is to extend the low jitter oscillator design methodology in several ways:
As stated earlier, investigation into 622MHz operation is a short term goal that will be partially supported by Analog Devices. The next SONET data transmission rate is 2.5GHz, which is a natural goal for the next stage of investigation. This is a suitable frequency for other reasons as well - a capability to 2.5GHz incorporates wireless communications such as cellular telephony at frequencies in the 800MHz to 1.9GHz range [11].
There are two ways to modify the ring oscillator design to allow operation at these higher frequencies: reduce the delay time of each gate, and reduce the number of gates in the ring. These steps inherently cause the simplifying assumptions to break down:
Assumption 1: As the dominant RC time constant is reduced to reduce delay and increase operating frequency, other delay mechanism such as carrier transit time and parasitic capacitances become significant contributors to delay. Representing the gate delay as being due to a single RC time constant is no longer feasible, and the theory will have to be broadened to take into account the effects of other significant delay mechanisms.
Assumption 2: As shorter ring lengths are used to achieve higher frequency operation, gate- to-gate interaction of jitter errors becomes more likely. The theory will have to be broadened to consider the effects of previous jitter errors on the jitter errors of succeeding delay stages.
Assumption 3: If there is gate-to-gate interaction, it is reasonable to expect that jitter will no longer be independent of the number of delay stages in the ring. The theory will need to be extended to incorporate the effects of rings of different lengths.
Will it be possible to express the results of this broadened theory in a simple enough fashion to preserve the intuition and insight offered by the simple theory? This is the major question to be addressed as the methodology is extended to higher speeds.
The original application for the simple theory was in a bipolar IC process. However the majority of ICs are fabricated in CMOS for cost reasons, even though the lower transconductance of MOS transistors make the CMOS process less technically suitable for analog tasks such as oscillator design. For the design methodology to be applicable to as many designs as possible, it is very important that it be extended to include CMOS. Development of the original theory was considerably simplified by assuming the oscillator signal to be much larger than the linear region of the differential pair (assumption 4). This "large signal" assumption is no longer true in the CMOS process, and the theory will need to be modified to take this into account.
The increasing emphasis on portable personal computing and communication [11] has intensified the drive to lower power, lower voltage integrated circuits. The simple theory was developed in a 5V-power-supply environment, where it was easy to meet the "large signal" assumption described above. As supply voltages shrink to 3.3V and below, however, there is less "headroom" for a large signal swing. As the oscillator signal amplitude is necessarily reduced, the "large signal" assumption breaks down.
The overall applicability of the theory has been demonstrated in the system-level application of data communication, in which the fundamental performance metric is a time-domain measure. Other applications, such as wireless communication and oversampled data conversion, have performance metrics in the frequency domain. To expand the proven fields of applicability of this theory, it will be necessary to fabricate ICs that perform system level functions in these fields. Then the ability of the theory to link performance across several levels of complexity can be verified in these other important application areas.
The method of this research will be to design and fabricate two general groups of integrated circuits: ICs that implement a system-level function and ICs with special purpose evaluation structures.
The goal of the special purpose evaluation ICs is to (as nearly as possible) isolate the assumptions of the basic theory to test where they break down, and illuminate how the theory needs to be modified and extended to capture circuit and system noise behavior at higher oscillator frequencies. The original methodology works at very well at low frequencies such as 155MHz where the simplifying assumptions hold. The simplifying assumptions trade off accuracy, but at low speeds the accuracy loss is modest and the bonus is a simple theory with intuitively pleasing results that provide a powerful guide to design. Pushing to the higher frequencies required by future applications (2.5GHz) inherently breaks these assumptions, and we can expect that significant modifications of the theory will be required.
The ICs that implement a system-level function are needed since the essential feature of the methodology is linking circuit level considerations to system-level performance. As the theory is modified, it is essential to verify the resulting design procedure by fabricating and testing prototype chips that implement a system function.
This research will be very valuable in extending and completing this design approach for ring oscillator design. With this extension of the methodology, design techniques for low-noise ring oscillators will be at the same level as techniques which are available for harmonic and multivibrator oscillators. Having a similar set of design tools for ring oscillators, which have been shown to have better performance than the multivibrator, would be a tremendous aid to the design of integrated communication systems. For example, a low noise design technique would be an indispensable resource for design of low phase noise oscillators for use in wireless communication ICs. The support of an industry partner such as Analog Devices is an indication of the direct value of this type of research to the technical community.
