- Interpolating ring VCO composed of differential pair gates (CMOS analogs of the 155MHz and 622MHz rings)
- A Current Controlled Oscillator (CCO) with single-ended inverter gates
- For each of the above, rings of different lengths (to test whether the design figure-of-merit in [1, 2] is also independent of ring length in CMOS)
- Clock-division circuitry to allow the basic ring architecture to span the required frequency range for the applications of interest
- Circuitry to duplicate interference coupled from on-chip digital signals, to test power supply rejection properties of each VCO circuit.
- How extensively does the bipolar jitter theory need to be modified in order to be applicable to CMOS differential pairs? The procedure in [1, 2] made use of simplifying assumptions that depend on the relatively high gain of the bipolar differential pair. These assumptions will probably have to be discarded in the case of the CMOS differential pair.
- Can the techniques of the theory be adapted to a single-ended CCO configuration?
- Just how much more sensitive is a single-ended delay stage to supply induced jitter?

Prof. McNeill's Ph.D. thesis [1, 2] investigated sources of noise in an integrated voltage controlled oscillator (VCO) used in a clock recovery phase-locked loop (PLL). A simple design technique was developed to establish correspondence among time and frequency domain measures of jitter with the PLL loop open or closed. Then the fundamental sources of jitter in a bipolar differential pair delay stage were identified, leading to a design procedure which gives explicit constraints on circuit elements as a function of desired system-level jitter performance. This technique has been verified accurate to within 10% in predicting system-level, closed-loop jitter over a 155MHz to 622MHz frequency range in the XFCB and XF1.5 dielectrically isolated complementary bipolar processes. There is considerable interest in extending these results into the corresponding CMOS circuitry for applications such as clock multiplication in digital modulator ICs. The research proposed for this fellowship would involve fabrication of ring VCO and basic PLL structures in single poly, 0.6µm 5V/3V and/or 0.35µm 3V processes. Possible test structures include:

Specific topics to be addressed include the following:

- Research
- Become familiar with existing designs
- Measure jitter on existing parts
- Check applicability of system level theory (e.g. noise / loop bandwidth relationship )
- Begin analysis of CMOS theory
- Based on analysis, define design work

- Design
- Detailed analysis
- Circuit design, simulation, layout

- Test
- Perform measurements on fabricated parts
- Document theory and results in M.S. thesis
- Transfer information to Analog Devices (e.g. brown bag seminar, etc.)

Based on preliminary discussions, the work would be divided into three phases - research, design, and test - as follows:

- J. McNeill,

"*Jitter in ring oscillators,*"

Ph.D. dissertation, Boston University, 1994. - J. McNeill,

"*Jitter in ring oscillators,*"

IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 870-879, June, 1997.

These pages by Chris David

2007/2/22