Analog IC Laboratory

The Analog IC Laboratory at WPI has been established in May 1998 as a state-of-the-art research and education facility for digital and mixed-signal integrated circuit design. The aim of the laboratory is to provide a comprehensive design environment for the development of novel integrated circuit and VLSI architectures, and to facilitate hands-on education of undergraduate and graduate students in all aspects of IC design. Various submicron fabrication technologies (including silicon foundries in the U.S., Canada and Europe) are currently being used for manufacturing the digital mixed-signal chips designed in the laboratory.


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CADENCE Design Tools in ECE Undergraduate Courses

ECE4902 Introduction to Analog IC Design is an undergraduate level course offered WPI, which introduces students to the design and analysis of analog integrated circuits such as operational amplifiers, phase-locked loops, and analog multipliers. Topics include:


Research Projects in Progress using CADENCE Design Suite

"Split ADC" Background Linearization of VCO-Based ADCS

In this project a lookup-table digital correction technique using ôSplit ADC?calibration is used for linearization of VCO-based ADCs. The ôSplit ADC?calibration approach enables a background LMS procedure that is tolerant of different input signals and provides calibration over the entire range covered by the input signal. Simulations are performed in 45nm and 180nm CMOS technologies.

Digital Background Calibration of Redundant Split-Flash ADC in 180nm CMOS

This project focuses on all digital background calibration of a redundant flash ADC in 180nm CMOS technology. All redundant comparators are used and correction is realized using a look up table which is continuesly calibrated in the background.

Design of a Sub-Picosecond-Jitter Delay-Lock-Loop for Interleaved ADC Sample Clock Synthesis

This work focuses on a design technique for generation of GHz ADC sampling clock phases from a low-cost low-frequency clock source. Jitter of order 0.1ps is enabled using a DLL-based frequency multiplication method. Nonidealities of the DLL approach are mitigated through digital background correction..

Layout for Redundant Flash ADC and DLL

An 8-b 1GS/s FLASH Analog to Digital Converter in 45nm CMOS Using the Self-Calibrating "Split-ADC" Architecture

This project focuses on calibration of a redundant Flash ADC using split ADC structure. Correction of errors and finding calibration parameters are all done in the background in the digital domain. This 8 bit flash ADC achieves the sampling rates of 1GS/s in 45nm CMOS.

Jitter in Ring Oscillators in 45 nm CMOS

This project investigates the relationship between short channel MOSFET width and the jitter/ phase noise in ring oscillators with the goal of exploring whether wider devices will produce lower jitter. Different CMOS ring oscillator topologies are designed and layed out in 45 nm SOI technology.

A 1MS/s Non-Linear Cyclic Analog to Digital Converter Using the Self-Calibrating "Split-ADC" Architecture

This project is to design and layout a 1MS/s Cyclic ADC and is an extension of the Self-Calibrating Cyclic ADC previously designed. This project takes advantage of the built in calibration due to the "Split- ADC" architecture and eases the linearity requirements of the residue gain block. This allows for a resistively loaded differential pair to be used instead of a 16-bit linear closed loop op-amp. Using this technique saves significant power, die area, and allows for a larger input signal range.

Layout for Cyclic ADC

A 12b 100MSps Pipeline ADC using the "Split-ADC" Architecture

This project is the design of a low-power 12-bit 100MSps pipeline analog-to-digital converter (ADC) with open-loop residue amplification using the novel "Split-ADC" architecture. The choice of a 12b 100MSps specification targets medical applications such as portable ultrasound. For a representative ADC such as the ADS5270, the figure of merit (FOM) is approximately 1pJ/step and the power dissipation is 113mW. The use of an open-loop residue amplifier resulted in a FOM of 0.571pJ/step and a power dissipation of 11.2mW.

Applying the "Split-ADC" Architecture to a 16 bit, 1MS/s differential Successive Approximation Analog-to-Digital Converter

Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CALDAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This project applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This project focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC.

Die Photo of Split-SAR ADC

Robust Thermal-Noise-Based Random Number Generation for Cryptographic Applications

Several emerging cryptographic applications (for example, smart cards and pervasive computing) require a low cost solution to the problem of obtaining random numbers for secure data communication. The source of random numbers should be well characterized in a statistical sense while being immune to potential tampering through non-random influences such as power supply. The project involves extension of previous VCO phase noise theory design of a phase-locked-loop (PLL) and a voltage-controlled oscillator (VCO) system to provide random numbers based on thermal noise. Previous verified techniques for maintaining immunity to power supply interferences will be used to ensure robustness of the system.

A Real Time Autonomous and Intelligent RF System

This project investigates the application of mixed signal techniques to design of a silicon germanium (SiGe) integrated circuit used in monitoring and control of an RF communication system in the 1-3GHz frequency range. A common problem in communication systems is detecting a small amplitude signal in the presence of a large amplitude interfering signal at a nearby frequency. If the frequency of the interfering signal is known, then a band-reject or "notch" filter can be used to cancel or attenuate the interfering signal. If the frequency of the interfering signal varies or is unknown, then the notch filter must be tuned to achieve optimum cancellation. One possible approach to this problem would involve the development of an intelligent microsystem that would sense the total signal amplitude in an RF frequency band, and adaptively tune a notch filter to cancel the largest amplitude signal.

Networked Electrophysiology Sensor-on-a-Chip

Our project will develop a mixed-signal integrated circuit (IC) prototype whose function is to provide complete, programmable analog conditioning and analog-to-digital conversion of an electrophysiologic signal. This IC will easily configure to small and large systems, be inexpensive, of small size, and require much less power than similar systems built from discrete components. These traits give this technology broad applicability to fixed, portable, and wearable sensor systems at all price/performance points. In particular, the technology is targeted for use in systems that acquire EMG (electromyogram), ECG (electrocardiogram) and/or EEG (electroencephalogram) signals.

Die Photo of Biomedical IC

Time Interleaved ADC Using the Self-Calibrating "Split-ADC" Architecture

Our project extends the split-ADC architecture and introduces the interleaved design theory to create a fully digital, deterministic, background calibrating ADC. This type of converter can quickly self-calibrate out errors, eliminating the need to wait a long time for accurate results. The design works by operating two ADCs simultaneously during every conversion cycle. The outputs of the two converters are stored and used to estimate what the value of the errors in the ADCs. These estimated error values are removed from the digital output code.

Layout for Time Interleaved ADC


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08/06/2016