Input Files

The two files generated by Xilinx M1 tools are time_sim.sdf, and time_sim.vhd. You will need these files in you simulation directory. The time_sim.sdf file contains all timing information that resulted from a specific place-and-route session. The time_sim.vhd is the simulation file that contains your design. This VHDL code looks nothing like the code you wrote because it is defined in terms of Xilinx CLBs and net connections. This means that it will be very hard and sometimes impossible to find the signals that you want to trace during this simulation.

In addition to your design files, some library components are needed. These are simprim_VITAL.vhd, <#949#>simprim_Vc