Post Place and Route Verification

The final step of the design process involves verification of your system after the place-and-route stage. Correct operation of the design can now be verified in the same manner as the register transfer level verification. During this stage, simulation is performed based on the timing information provided by the Xilinx place-and-route tools. This information includes the net, CLB, and pad delay that were incurred during the place-and-route stage.